systolic array
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网络 脉动阵列; 阵列机; 阵列处理; 脉动式阵列; 收缩阵列
双语例句
- To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。 - Nonlinear Power Amplifier Modeling Based on QR-RLS Systolic Array
基于QR-RLS脉动阵列的非线性功放建模 - A circuit structure with systolic array is introduced in this paper in order to accelerate the speed of matrix inversion, which is quite prone to implement.
为加速矩阵求逆，研究构造出一种非常易于实现的基于心动阵列的矩阵求逆的电路结构。 - A Normal Method for Mapping Montgomery Algorithm into a Systolic Array
蒙哥马利算法到脉动阵列的规范映射方法 - The realization of mapping a class of nested loop algorithms to linear systolic array is studied.
研究了一类多重循环算法的线性脉动阵列实现。 - Study of Mapping from IMM Algorithm to Systolic Array
IMM算法到systolic阵的映射研究 - This paper presents a kind of systolic array architecture which is used to realize BP algorithm. It designs a characters recognition system in FPGA based on this systolic array architecture.
提出了一种用于实现BP神经网络的串行输入串行输出的脉动阵列结构，在FPGA上实现了基于该阵列结构的用于进行A-Z的印刷体字符识别系统。 - Steady State Analysis and Realization of the GSC Adaptive Antenna System with a Systolic Array
Systolic阵结构的GSC自适应天线系统稳态分析与系统实现 - A hybrid systolic array for the realization of the discrete Fourier transform is proposed.
本文提出混合递进阵列（HybridSystolicArray）的概念以及用混合递进阵列实现高阶离散傅立叶变换的方法。 - In this paper, a technique and its implementation are discussed for automatic generation of Systolic array algorithms from sequential algorithms. In practice, this technique is feasible.
本文论述了由串行算法自动生成Systolic阵列算法的一种技术及其实现，实践表明这一技术是可行的。 - Finally some design methods of Systolic array are presented.
最后，概述了Systolic阵列的设计方法。 - Realization of BP Algorithm in FPGA Based on Systolic Array Architecture
BP算法的脉动阵列结构在FPGA上的实现 - A method of decreasing data width between cache and systolic array on motion estimation chip
运动估计芯片中降低局存与脉动阵列数据宽度的设计方法 - On the correctness and optimization of systolic array algorithms
一类脉动阵列算法的正确性与最优性 - In this paper, we use a multiuser detection based on systolic array, this systolic architecture adaptively reconfigures the tap coefficient of the transversal filter, through comparing it with other detection, the conclusion is drawn that the detector has high performance.
本文采用了一种脉动阵列多用户检测器，它采用脉动阵列结构，能够自适应地调整横向滤波器的抽头系数，与其他检测器比较，它具有较好的性能。 - Systolic Array Implementation of DCT, DHT and DFT
DCT，DHT与DFT脉动阵列实现 - A real-time wave-front reconstruction processing method based on FPGA with systolic array is proposed according to the characteristics of wave-front reconstruction algorithm.
根据波前复原算法的特点，提出了用脉动阵列实现基于FPGA的实时波前复原处理方法，采用流水和并行处理技术，提高系统的吞吐率； - The theory about a merging sorting algorithm-insert merging is presented in this paper. Through the mapping it into systolic array, the realizing method of VLSI array by canonical mapping is proposed focuses.
本文介绍一种归并排序算法&插入归并算法的基本原理，并通过该算法的Systolic阵列映射，重点阐述了正则映射生成VLSI阵列的理论和方法。 - A normal method is introduced for mapping the algorithm into a systolic array.
该文介绍蒙哥马利算法到脉动阵列的映射过程，阐述了从算法到脉动阵列的规范映射方法。 - The paper gives a three dimensional DFT example which is implemented by cube-vector method in systolic array.
文章还给出了在Systolic阵列上由方体向量法实现的三维DFT的具体例子。 - To obtain the highest data reuse efficiency and minimum I/ O pin count while achieving 100% hardware efficiency, a systolic array and full pipeline architecture is adopted.
通过脉动阵列和全流水线的设计，达到最高的数据重用率、最小的I/O引脚数和100%的硬件计算效率。 - Among MC_DCT, computational complexity is reduced based on using approximate matrices. Parallel design and systolic array structure is adopted in the overall design in this paper.
针对MCDCT中的矩阵乘法，本文设计了一种适合硬件实现的快速方法，在整体设计上采用了并行流水和脉动阵列的结构； - In this paper, we preset the processing elements based on a special butterfly computation and discrible the systolic array implementations for computing DCT, DHT ( DWT) and DFT respectively.
文中绐出了两种基于特殊蝶形运算的处理单元和两种计算DCT，DHT（DWT）和DFT的脉动阵列实现。 - Systolic Array and Its Application to Pattern Recognition and Image Processing
Systolic阵列及其在模式识别与图象处理中的应用 - Researches on multidimensional DFT cube-vector method in systolic array
Systolic阵列中的多维DFT方体向量法研究 - A new square-root formation of linear quadratic optimal control algorithm is proposed, and the algorithm is mapped to parallel architecture-systolic array.
文中提出了一种平方根线性二次型最优控制算法，并将其映射到并行专用结构&脉动阵列（systolicarray）上。 - A fine-grained mapping approach is proposed according to the analysis of the detailed configurable logic block structure of FPGA device, and it is applied to the design of a systolic array for modular multiplication based on FPGA.
通过分析FPGA可配置逻辑块的细致结构，提出了一种基于FPGA的细粒度映射方法，并使用该方法高效实现了大数模乘脉动阵列。 - Then a systolic array Multiplier is discussed. At last, structure of the 3D accelerating graphics engine is analyzed.
本文然后讨论了脉动矩阵乘法器的设计，最后讨论了3D几何图形加速引擎的结构。 - In the third chapter, through the derivation of systolic array design demonstrates the feasibility of the method can be configured.
在第三章中通过推导，论证了脉动阵列设计的可配置方法的可行性。 - Secondly, systolic array Multiplier is designed which can speed up the multiplication of two matrices.
其次本文设计了脉动矩阵乘法器，用于加快两个矩阵的乘法运算。